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Samsung Leapfrogs Toward 1000-Layer NAND With First 900-Layer V-NAND Prototype, Stacking Two 450-Layer Cells Into One
1+ hour, 28+ min ago (247+ words) Samsung is getting closer to its 1000-Layer V-NAND tech as it achieves the first 900-Layer prototype, bracing for swift competition with rivals. Samsung is a pioneer in storage semiconductors. Its V-NAND technology is seen as one of the best on…...
" Scaling Law Introduced at ISCAS 2026: Huawei Proposes Time-Based Semiconductor Scaling Beyond Moore's Law
5+ hour, 36+ min ago (172+ words) Southeast Asia Smartphone Shipments Decline ASP Growth Drives Market Shift...
Corsair DDR5 RAM Spotted With Chinese CXMT Memory as Global DRAM Shortage Expands
2+ day, 18+ hour ago (229+ words) According to images shared by leaker wxnod, Corsair has started using memory chips from Chang Xin Memory Technologies, also known as CXMT, in some of its DDR5 modules. Corsair has traditionally relied on major Korean memory suppliers, so this move stands…...
Huawei proposes "Tau Law" as alternative to Moore's Law, first logic-folding chip arrives this autumn
8+ hour, 40+ min ago (72+ words) Huawei proposes "Tau Law" as an alternative to Moore's Law, aiming at 1. 4nm-level performance. First Kirin chip launches this autumn....
At an IEEE conference, Huawei proposed a new chip scaling law and said it aims to design chips with transistor density equivalent to 1. 4nm by 2031
9+ hour, 8+ min ago (68+ words) Nikkei Asia: At an IEEE conference, Huawei proposed a new chip scaling law and said it aims to design chips with transistor density equivalent to 1. 4nm by 2031 This is a Techmeme archive page. It shows how the site appeared at 11: 50 PM…...
i Catch Technology Showcases HSB-Aligned Imaging ASIC PAISB at COMPUTEX 2026
11+ hour, 55+ min ago (426+ words) digitimes i Catch Technology Showcases HSB-Aligned Imaging ASIC PAISB at COMPUTEX 2026 i Catchtek Showcase PAISB at COMPUTEX 2026. Credit: i Catchtek i Catch Technology announced PAISB (Physical AI Sensor Bridge) - a HSB-aligned Imaging ASIC designed to enable scalable, time-aligned multi-sensor ingest…...
AI Memory Shortage: AMD's Lisa Su Identifies High-Bandwidth Memory as AI Chip Supply's Next Cap
21+ hour, 29+ min ago (492+ words) That constraint is now easing. TSMC's Co Wo S output reached approximately 75, 000 wafers per month in 2025, and analysts at Trend Force project further expansion to 120, 000 monthly by the end of 2026 through capacity additions at its AP6, AP7, and AP8 advanced packaging facilities. Nvidia's…...
Embedded substrates draw AI chip interest as packaging turns strategic
13+ hour, 26+ min ago (119+ words) digitimes Embedded substrates draw AI chip interest as packaging turns strategic Keep me signed in - Track financials & stock data of Taiwan tech. - Agibot claims 100% success rate in factory deployment as humanoid race shifts to real-world validation - SK Hynix speeds Yongin…...
Micron Technology (MU) Current Structural Analysis " May 24, 2026
1+ day, 4+ hour ago (10+ words) Moomoo...
AI server boom lifts memory interface chip leader, but DDR5 risks linger
13+ hour, 24+ min ago (146+ words) digitimes AI server boom lifts memory interface chip leader, but DDR5 risks linger Montage Technology, a company that does not manufacture memory chips itself but instead supplies the interface chips linking CPUs and memory, has quietly emerged as one of the…...